(1) Technical Field
This invention involves integrated circuit packaging structures and methods for microwave integrated circuits, and related integrated circuit testing methods.
(2) Background
In typical semiconductor fabrication systems, integrated circuits (IC) dies (also known as “chips”) are built up in large numbers on a single large wafer of semiconductor material, and then eventually cut out of the wafer (“singulated”) as individual dies. Such ICs are generally either sold in bare die form or in packaged form (e.g., plastic packages). However, handling a conventional IC part in bare-die form is difficult for a typical customer, because clean room facilities are required to assemble the die into a chip-and-wire hybrid assembly and specialist pick-and-place machines are required for “bumped” die. Accordingly, many customers would prefer receiving packaged microwave ICs from vendors. One drawback of using packaged ICs is that the package degrades the microwave performance of the part due to unwanted (parasitic) electrical effects such as bond-wire inductance.
An important aspect of packaging and testing conventional microwave ICs is limiting the effects of external influences and uncompensated parasitic influences (e.g., parasitic inductances and capacitances) on the designed microwave circuitry embodied on an IC die. One way to do so is to provide ample ground connections to sensitive circuit elements and limit the electrical length of such connections.
Most microwave ICs on the market today are fabricated on substrates made from rather exotic compounds from the III-V group of semiconductors (e.g., gallium arsenide), which allow the fabrication of through-hole vias (i.e., holes piercing select areas of an IC die) to achieve low inductance ground connections on one surface of a die to selected locations on the other surface of the die. Such vias connect directly to the back surface of a III-V material IC die, and the back surface is electrically connectable directly to a circuit ground plane. The presence of through-hole vias and backside grounding allows a conventional microwave IC die to be tested using automated wafer-probe technology. After testing, validated dies are generally packaged for use by customers, with the attendant drawbacks noted above.
Disadvantages in using III-V materials for IC dies include toxicity of the materials and greater cost relative to IC dies made on silicon or on silicon-on-insulator (SOI) substrates (including but not limited to silicon-on-sapphire, or “SOS”, substrates). However, typical silicon or SOI IC dies do not have the capability to form through-hole vias. Such ICs therefore rely on wire-bonds at the outer edge of a die or “flip-chip” packaging to provide grounding.
With wire bonding, a die is mounted upright in a carrier package or on a circuit board or another chip or wafer, and wires are used to electrically and mechanically couple connection pads on the edges of a die to external connector pins or circuitry. Wire-bonding is deficient at high radio frequencies (e.g., greater than about 8 GHz) because the wire-bonds have significant length and therefore inductance, which limits grounding effectiveness. Further, ground connections are limited to edges of a die; accordingly, circuit elements located away from the die edges may not be adequately grounded and/or parasitic circuit influences may be created by running conductive traces from the IC pads to the interior of the die. Such grounding problems with wire-bonded silicon or SOI dies means that automated wafer probing cannot be easily implemented, resulting in problems of verifying performance at microwave frequencies. Further, in packaged form, the parasitics of the package cause degradation of microwave performance, through bond-wire inductance in both signal and ground connections, and imperfect signal routing from a bond-wire to the exterior of the package. Moreover, testing of a packaged device generally requires a socket or fixture that leads to uncertainty and unreliability of the test results, since the test socket or fixture is not part of the final product shipped to a customer and generally adds parasitic factors to the circuit under test.
To overcome the grounding and testing issues with wire bonding, “flip-chip” packaging and processing may be used for some applications. “Flip chip” processing (also known as controlled collapse chip connection or its acronym, C4) is a method for interconnecting IC dies to external circuitry. FIG. 1A shows a single integrated circuit die 100 having a grid of metalized connection pads 102 on the top surface; multiple dies would be simultaneously formed on a silicon or SOI wafer. FIG. 1B shows the IC die 100 of FIG. 1A with solder bumps 104 deposited onto the grid of connection pads 102. The solder bumps are usually deposited on the pads on the top side of each die of a wafer during the final wafer processing step. In order to mount a die to an external circuit structure (e.g., a circuit board or another chip or wafer), the wafer is singulated into dies, then each die is flipped over so that its top side faces down and aligned so that its pads align with matching pads on the external circuit structure. FIG. 1C shows the IC die 100 of FIG. 1B flipped and positioned so that the solder bumps 104 are facing a matching set of connectors 106 of an external circuit structure 108. FIG. 1D shows that the solder bumps 104 of the IC die 100 of FIG. 1C are then re-melted (typically using hot air reflow) to complete the interconnection. The mounted die may then be under-filled using an electrically-insulating adhesive to provide a stronger mechanical connection, provide a heat bridge, and to ensure the solder joints are not stressed due to differential heating of the chip and the rest of the system.
The resulting completed flip chip assembly is much smaller than a traditional carrier-based system; the chip can sit directly on a circuit board, and is much smaller than a carrier package in both area and height. The many short solder bump connections greatly reduce inductance, allowing higher-speed signals, and also conduct heat better. Further, automated wafer-probe technology can be used to test a flip chip while the connection pads are exposed.
However, flip chip processing has several disadvantages. Customer manufacturing processes may not be compatible with flip chip assembly, which requires special handling equipment to pick and position the singulated dies, as well as to perform the reflow process. Accordingly, flip chip microwave ICs fabricated on silicon or SOI wafers are not suitable for many customers.
The limitations of both wire-bonded packaging and flip chip assemblies are a primary hindrance to the use of silicon-based IC technology at microwave frequencies. The present invention addresses this problem.